PCB impedance calculator: USB 90 Ω, 50 Ω, 100 Ω pairs
Pick the structure, give it your stack-up, and get the trace width for a target impedance, or the impedance of a width you already drew. Built for the common question: what width and gap give a 90 Ω USB 2.0 pair on a 4-layer board.
The first value on screen is a closed-form estimate for bare copper; it is replaced within a moment by a 2-D finite-difference field solution (Laplace’s equation solved twice, with the real dielectrics and in vacuum, then Z0 = 1/(c·√(C·C0)), the standard quasi-static method; pairs from the even and odd modes). Measured 2026-10-15: against OSH Park’s published 4-layer impedance table (docs.oshpark.com; 0.6 mil resist, mask Er 3.3 assumed) the solver is +1.05 % on the 50 Ω single trace, +0.81 % on the 90 Ω pair and +1.05 % on the 100 Ω pair (3.0 to 3.8 for the mask Er gives 50.1 to 50.4, 91.5 to 92.7 and 100.4 to 102.0 Ω); the bare-copper closed forms read +3.9 %, +9.7 % and +10.3 % high on the same table because they ignore the mask. Without mask the solver agrees with Hammerstad–Jensen and Kirschning–Jansen to within 1.95 % for w/h 0.5 to 3. Against Cohn’s exact result for a zero-thickness stripline it is within 0.87 %. Doubling the grid density changes results by at most 0.46 % and doubling the open-boundary distance by 0.13 %. The model is an electrostatic cross-section: no frequency dispersion, rectangular copper. Confirm with your fab’s impedance calculator (for JLCPCB: jlcpcb.com/pcb-impedance-calculator) and check the stack-up on your order.
Sources: method: quasi-static field solution with and without the dielectric, Steer, Microwave and RF Design II, section 3.5 Microstrip Transmission Lines (eng.libretexts.org), D. M. Pozar, Microwave Engineering, chapter 3, and the finite-difference practice in the University of Houston ECE 3318 project; solver written for this page (no MIT or BSD JavaScript solver exists; atlc, KiCad, Qucs and openEMS are GPL and were not copied). Instant estimate and cross-checks: Hammerstad and Jensen, “Accurate Models for Microstrip Computer-Aided Design”, IEEE MTT-S 1980; Kirschning and Jansen, “Accurate Wide-Range Design Equations for the Frequency-Dependent Characteristic of Parallel Coupled Microstrip Lines”, IEEE Trans. MTT 1984 (static even and odd mode, with the strip-thickness correction of Jansen), as printed in the Qucs Technical Documentation, chapter Microstrip components; S. B. Cohn, “Shielded Coupled-Strip Transmission Line”, IRE Trans. MTT 1955, as printed in Rogers Corporation design note 3.2.1; B. C. Wadell, Transmission Line Design Handbook, Artech House 1991; IPC-2141A, Design Guide for High-Speed Controlled Impedance Circuit Boards, 2004; Johnson and Graham, High-Speed Digital Design, 1993. Solder mask defaults: Rogers Corporation, “Finding the right solder mask for RF/microwave PCBs” (Dk 3.3 to 3.8) and the Florida CirTech LPI 950 LC-1 data sheet (15 to 20 µm). Stack-up numbers, read 2026-10-15: PCBWay multi-layer laminated structure page (prepreg Dk and thickness after lamination); OSH Park 2-layer and 4-layer service pages (docs.oshpark.com, including the 0.6 mil resist); JLCPCB capabilities (Er) and the JLCPCB impedance templates as published in github.com/gsuberland/jlcpcb_autogenerated_stackups (auto-generated, third party, not verified by JLCPCB).
The formula
Single microstrip: Hammerstad–Jensen (1980) with the finite-thickness correction (Wadell) Single stripline: Z0 = 60/√Er · ln(4b / (0.67π(0.8w + t))) Pair: Zdiff = 2·Z0·(1 − 0.48·e^(−0.96·s/h)) microstrip, 2·Z0·(1 − 0.347·e^(−2.9·s/b)) stripline
When to use it
Use it when a spec asks for a controlled impedance: 90 Ω differential for USB 2.0, 100 Ω for Ethernet, LVDS and many serial links, 50 Ω single-ended for RF and clocks. On a 4-layer board the top signal layer sits on a thin prepreg over the first inner plane, so the dielectric height h is the prepreg thickness, usually 0.1 to 0.21 mm, and a 90 Ω pair comes out a practical 0.2 to 0.3 mm wide. On a 2-layer board h is the whole 1.5 mm core, so the same impedance needs traces a bit over a millimetre wide, which is why short USB 2.0 runs on two layers are usually just routed as a tight pair of equal length without chasing 90 Ω. Give the fab your target, not just your widths: the fab adjusts to its own stack-up.
Pitfalls
- The number you see after “solving” is a 2-D numerical field solution of your cross-section, accurate to about 1 % of an exact answer and within about 1 % of OSH Park’s own published impedances (measured, see below). That is the accuracy of the model, not of your board: fab etch, laminate tolerance (OSH Park quotes ±10 % on prepreg thickness) and the real mask Er move the real impedance by several percent. Ask the fab to confirm with its own impedance calculator before you commit, and use what it gives you for the final widths.
- The reference plane must be continuous under the whole pair. A split or a slot in the plane under the trace changes the impedance more than any rounding in this calculator does.
- Solder mask is modelled as a conformal film of the thickness and Er you give, over the copper and in the gaps; its Er is rarely published, and 3.0 to 3.8 changes a 90 Ω pair by about ±1 Ω. Etched traces are trapezoids, narrower on top than at the copper face; the model uses rectangular copper, so a heavily undercut trace reads a little low.
- Each preset uses the dielectric height, Er and copper thickness its manufacturer publishes (the JLCPCB 4-layer rows come from a third party). Fabs quote Er at different test frequencies, other copper weights and prepreg choices differ, and the fab may change the stack-up for your order. Pick Custom and type your own.
- Tight coupling makes the pair more sensitive to etch tolerance in the gap. If the solved width comes out narrower than your fab’s minimum trace, widen the gap or ask for a thinner prepreg instead of squeezing the trace.
Related note
USB-C power delivery for a non-phone productNeed a USB or high-speed board laid out with the impedance checked against the fab’s stack-up?