PCB layout mistakes that show up at assembly

The board passed DRC, the fab made it without a question, and the first thing the assembler says is that they cannot run it. The fiducials are under a connector, half the parts in the placement file are rotated, and the board is too small to go through the line on its own. None of that is an electrical fault. All of it stops the job.

These are the layout details that a fabrication house never checks, because they do not affect drilling or etching. They only matter once a pick-and-place machine has to find the board, put a part on it, and get the orientation right. Here is what goes wrong and how to catch it before the job leaves your desk.

Fiducials belong to the machine, not the board

A pick-and-place machine locates the board optically before it places anything. It looks for fiducials: bare copper dots with a clear ring of solder mask around them, at known coordinates. If it cannot see them, it either refuses the panel or places every part with an offset it has no way to detect.

Two mistakes recur. The first is leaving the fiducials off because the board is small and there is no room. The second is putting them where a component will cover them. A KiCad forum thread has a designer asking whether fiducials can sit inside the courtyard of a large part, and the answer from people who run lines is that this is a manufacturing question rather than a design one. If the first pass places a part over the fiducial, the second pass has nothing to look at. That matters on any board with both sides populated, and it matters on a single-sided board if the machine re-registers between feeders.

The usual resolution is the same one that thread reaches: a small board goes into a panel, and the fiducials go on the panel rail where nothing will ever cover them. Sierra Circuits publishes its own panel requirements for assembly, including fiducial sizes and edge clearances. Treat numbers like those as one assembler’s rules, not as a universal standard. The assembler you actually send the job to will have their own, and the right move is to ask for them before you draw the panel, because a rail that is too narrow for their conveyor or a fiducial that is too close to the edge for their camera means a second fab run.

Fiducial footprints also need the right attributes. In KiCad they should be excluded from the bill of materials, and whether they appear in the placement file depends on what the assembler wants. The KiCad PCB editor manual documents the per-footprint “Exclude from position files” and “Exclude from bill of materials” attributes for exactly this purpose. A fiducial that shows up as a line item with no part number is a small thing, but it is the kind of small thing that triggers a clarification email and costs a day.

Panels and what the line has to hold

A bare board that is too small, too oddly shaped, or has parts right up to its edge cannot be carried through a reflow oven and a placement machine on its own. The panel solves that, and the panel is a design object with its own failure modes.

The rails are where the conveyor grips the panel, so they must be free of components on both sides and wide enough for the assembler’s equipment. Tooling holes on the rails let the machine pin the panel in a repeatable position. Fiducials, as above, go on the rails. The boards inside the panel connect through V-scores, breakaway tabs with mouse bites, or a mixture, and each of those interacts with what is near the board edge. A V-score is a straight cut across the whole panel, so it cannot stop short of a connector that hangs past the outline. Mouse-bite tabs leave a rough edge where they break, so they should not land where the board mates with an enclosure or where a component sits within reach of the break.

You do not need to draw any of this by hand. KiKit is a free tool for KiCad that generates a panel from a single board file with rails, tabs, mouse bites or V-cuts, tooling holes and fiducials, all as command-line parameters. Its examples show fiducials and tooling holes being placed on the frame with explicit offsets and sizes, which is the form an assembler’s guideline takes. Doing it in a script rather than by hand means that when the assembler comes back with a different rail width, you change one number and regenerate.

One thing KiKit cannot know is what the assembler’s depaneling equipment can do. Ask whether they V-score, route, or break by hand, and design the tabs for that.

Courtyards are the placement head’s reach

KiCad footprints carry a courtyard outline: the area the part and its placement tolerance occupy, drawn on a dedicated layer. The design rule checker flags overlapping courtyards. It is tempting to treat those warnings as advisory and pack parts closer, and on a hand-assembled prototype that often works. On a line it fails in two ways.

The first is mechanical. The nozzle that places a tall part needs clearance around it to descend and release, and the rework operator who has to lift a QFN needs room for a hot-air nozzle that is wider than the part. Two courtyards that touch may still be placeable, but two that overlap by a fraction of a millimeter at a decoupling capacitor next to a shielded inductor are the first thing an assembler marks up.

The second is inspection. Automated optical inspection looks at each joint from an angle. A tall part right next to a small one shadows the small one’s fillets. Then the inspection system flags parts that are fine, and someone has to look at every one by hand. Keep the tall parts together, and keep the short parts where the camera can see them.

If your library footprints have courtyards drawn to a convention, and KiCad’s official library does, then the DRC warning is meaningful and worth clearing rather than suppressing. If you drew the footprint yourself and skipped the courtyard, the check is silently disabled for that part, which is worse than a warning.

Polarity, pin 1 and the placement file

The placement file, also called the centroid or pick-and-place file, gives the assembler a reference designator, an XY position, a rotation and a side for each part. It looks trivial. It is where most orientation errors come from.

The rotation in that file is relative to the footprint’s zero orientation, and the zero orientation is whatever the footprint author chose. A diode drawn with the cathode on the left and one drawn with it on the right produce identical boards with different rotation values. Assemblers know this, and they visually check every polarized part against the silkscreen and the fab drawing. That means the silkscreen has to make the answer unambiguous: a pin-1 dot that survives being partly under the part, a cathode bar on every diode, a plus sign on every polarized capacitor, and a pin-1 chamfer or dot on every connector. Digi-Key’s PCB best practices put it plainly: label reference designators and orientation on the silkscreen, and keep silkscreen off the pads.

The KiCad manual also documents two placement-file options that regularly bite. The first is “Include only SMD footprints”, which uses each footprint’s fabrication attribute. A footprint left as “Unspecified” is neither through-hole nor SMD and drops out of an SMD-only export with no warning, and the assembler is then missing a part they can see on the board. The second is the origin. The placement file can be referenced to the page corner or to a drill and place origin you set on the board, and if you send the assembler a file measured from one and a drawing measured from the other, every part is offset by the same amount and nothing lines up. Set the origin to a board corner or a tooling hole, use the same origin for the drill file, and say which one it is in the readme.

One more attribute matters here. KiCad lets you mark a footprint “Do not populate” separately from excluding it from the BOM. A part that is on the board but not fitted on this build should be in the BOM as DNP and omitted from the placement file, or included and flagged, depending on what your assembler asks for. Sending it with no flag at all is how a part gets fitted that should not be.

The check before you send it

Before the package goes out, we run through the same short list on every board that is going to a line for the first time:

Item	What to look at
Fiducials	Present, on the rail or in clear corners, nothing covering them on either side, excluded from the BOM
Panel	Rails on the sides the conveyor uses, tooling holes, tabs or V-scores that clear connectors and the enclosure fit
Courtyards	DRC clean or each overlap deliberately reviewed, tall parts grouped, nothing shadowing small parts
Silkscreen	Pin 1, cathode and polarity on every part that has one, designators readable after placement, nothing on pads
Placement file	Every footprint has a fabrication type set, origin matches the drill file, DNP handled the way the assembler wants
Paste layer	Every SMD pad has an aperture, thermal pads follow the package vendor’s stencil guidance rather than a full-pad opening

That last row deserves a sentence. The solder paste layer in your Gerbers becomes the stencil, and a large exposed pad under a QFN opened as a single aperture will float the part on excess solder and starve the perimeter pins. Package vendors publish mounting notes with segmented aperture patterns for their thermal pads. Use the note for the actual package, because the recommendation differs by part.

None of this is difficult. All of it is invisible to the fab, invisible to DRC unless the library is disciplined, and expensive when discovered by the assembler. If you are sending us a board for its first assembly run, include the placement file, the fab drawing with the origin marked, and a note on which parts are polarized — see our note on what to send for a PCB assembly quote for the full package — and we will check the rest against this list before anything is ordered.