Where to put ESD protection on a USB or connector port

A board passes every bench test. Then someone walks across a carpet, touches the USB shell, and the device resets, drops its link, or never comes back. The schematic has a TVS diode on the connector, so the protection is “there.” It still fails.

That happens more than it should. The part is on the schematic, but the layout decides whether it works. This note covers where the protection goes, how it connects to ground, and what to keep out of its way.

What the protection part actually does

An ESD event at a connector is a very fast, high-current pulse. A TVS diode clamps the line to a safe voltage by shunting that pulse to ground. The pulse has to reach the diode before it reaches anything else, and it has to leave through a low-impedance ground path.

Most of the problem is inductance, not the diode itself. Texas Instruments’ TVS ESD layout guide says it plainly: minimize the inductance between the ESD source and the path to ground through the TVS, and the inductance between the TVS and ground is critical. Every millimeter of trace and every via adds some. A fast pulse across even a little inductance produces a voltage, and that voltage lands on whatever sits downstream.

So a TVS with the right standoff voltage and a poor layout can protect much less than its datasheet suggests. The datasheet number assumes a good connection.

Placement: the diode goes at the connector

The rule from the same TI guide: place the TVS as near to the connector as design rules allow, with the protected IC much farther from the TVS than the TVS is from the connector. The TPD4E1U06 datasheet layout section repeats the point for that part: the optimum placement is as close to the connector as possible. Semtech’s USB 2.0 protection note says the same for D+, D− and VBUS.

Three habits follow from this.

Route through the diode, not past it. The protected line should run from the connector pad straight to the TVS pad. Do not tee off a stub to the diode. TI says to avoid stubs between the TVS and the protected line and to route directly from the ESD source to the TVS. If the signal goes to the MCU first and the diode hangs off a branch, the pulse takes the shorter path, which is into the MCU.

Keep unprotected copper out of the zone. TI advises not routing unprotected circuits in the area between the ESD source and the TVS. A pulse on the connector side radiates. A neighboring trace that goes to a sensitive input will pick it up, even though the real conductor is clamped.

Avoid vias and sharp corners on that short run. Where a via is unavoidable, TI says to go directly from the source to the TVS before changing layers. Straight traces are preferred, and corners should be rounded rather than sharp, because fields build up at corners and increase coupling. The TPD4E1U06 datasheet gives the same advice.

Grounding: where most boards go wrong

The diode’s ground pin is half of the clamp. TI’s guidance is to connect the TVS ground directly to a same-layer ground plane that has nearby vias stitching to an adjacent internal ground plane, and to use large-diameter vias because they lower impedance. It also recommends tying a chassis screw to PCB ground near the TVS and the connector, where the enclosure allows it.

What that means in practice:

• Put the ground via at the TVS pad, not a few millimeters away at the end of a thin trace.
• Use more than one via where the pad can take them.
• Give the pulse a plane to spread into, not a narrow neck.
• Do not put a series element in the ESD return path. A ferrite bead or a long thin ground trace between the connector shell and the board ground adds exactly the inductance you are trying to remove. A bead is fine as a filter on a power or signal line. It is a poor choice as the route for a static pulse.

Shield and shell handling is a design decision with trade-offs. Tying the shell straight to ground gives the pulse the easiest path. Some products isolate the shell through a resistor and capacitor network for noise or safety reasons. Whichever you choose, decide it on purpose and test it. Do not inherit it from a reference design without reading why it was done that way.

Which lines need protection

For a USB 2.0 port, Semtech’s note lists VBUS, D+ and D− as the lines to protect. They are different jobs:

• VBUS carries power, so the clamp has to cope with a power rail. Pick a part with a working voltage above the highest voltage the port can legitimately see. On a USB-C port that negotiates higher voltages, see our note on USB-C Power Delivery input before picking a standoff voltage.
• D+ and D− carry data. A diode with too much capacitance rounds the edges and can break signal integrity. Semtech’s examples for this job are specified in the low single-digit picofarad range or below, and that capacitance figure belongs in your part selection, not as an afterthought. Check the datasheet for the speed you actually run.
• CC, SBU and other USB-C pins are exposed to the same event. If they reach the MCU or a PD controller, they need a look too. Check what the controller’s own datasheet claims for its pins before assuming it protects itself.

The same reasoning applies to any exposed connector: a button, a sensor input, a UART header that ends up on a panel, an Ethernet jack. If a human can touch it, treat it as an ESD entry point.

Why the failures look strange

ESD problems rarely announce themselves. Typical symptoms:

• A reset or brownout when the connector is touched. Our note on finding why a device resets in the field covers how to tell this apart from a power problem.
• A USB link that drops and needs a replug.
• A peripheral that stops responding until power-cycled, which points to a latch-up or a corrupted state, not a clean fault.
• A part that works for a while, then fails weeks later with no obvious cause. Damage from an event that was survived, but not cleanly, can show up later.

These are hard to reproduce, which is why engineers get stuck. A device that survives ten zaps may still fail on the eleventh because the pulse arrived at a different point on the shell.

What a careful review checks

When we look at a design with an exposed port, the checklist is short.

1. Is the protection part the first thing on the line after the connector pad, with no stub?
2. How long and how wide is the ground return from the diode to the plane, and how many vias carry it?
3. Is any unprotected trace running through the zone between the connector and the diode?
4. Does anything in the ground path add inductance, such as a bead, a thin neck or a split plane?
5. Is the diode’s working voltage and capacitance right for this line, from the datasheet?
6. Does the enclosure give the discharge somewhere to go other than the electronics?

Then it needs a test. Simulation does not replace discharging a real board with a real tool at the real connector. Plan that into your compliance testing early, because a layout change after a failed test costs a board spin. If your product will be tested to an ESD level for sale in a particular market, find out which level before the layout is frozen, not after.

What we do

We read the schematic and layout around every exposed connector, mark where the pulse will travel, and fix the placement and ground path in KiCad. Send us the schematic, the board files and a note on which connector fails and how, and we will tell you what we would change.

Sources: TI SLVA680A, TVS ESD diode layout guidelines · TI TPD4E1U06 datasheet, layout · Semtech, ESD protection of USB 2.0 interfaces