Checking KiCad fabrication files before you send them

The board passes DRC. You plot Gerbers, zip the folder, upload it, and a day later the fab asks which file is the board outline. Or worse, nobody asks, and the boards arrive with a stale copper pour or a part rotated ninety degrees.

Almost none of these problems are design errors. They are release errors: the files that left the project did not match the project. This note is the check we would run between “layout done” and “upload”, for KiCad projects specifically.

Start with the project, not the files

Every output is generated from the board as it exists at that moment. If the board is out of date, every file is out of date with it.

Refill the zones. KiCad’s documentation says it is important to make sure zone fills are up to date before generating outputs, and that KiCad will warn you when zones have not been refilled. Treat that warning as a stop sign, not a nuisance. A pour that was filled before the last routing change can short a net or leave a gap that the on-screen view hides.

Run DRC with the schematic parity check on. DRC finds clearance and minimum-width violations, unconnected nets and other rule problems. The parity check compares the board against the schematic, which catches the case where someone edited the schematic and never ran Update PCB from Schematic. The KiCad PCB Editor manual covers both. Fix errors. For each warning you decide to keep, know why.

Check the rules are yours. DRC only enforces the constraints in the board setup. If the project still carries default rules from a template, a clean DRC means “clean against someone else’s numbers.” Compare the setup against the fabricator’s published capabilities for the process you chose. Those capabilities are specific to each supplier and each stackup, so read the ones for the house you are actually using.

What goes into the Gerber set

The plot dialog has a handful of options that quietly change what the fab receives. The ones worth deciding on purpose:

• Gerber X2 format. X2 embeds metadata in each file, including a file-function attribute that says whether a file is top copper, bottom solder mask, legend and so on. Ucamco, which maintains the format, describes attributes as meta-information about the image, such as whether an object is an SMD pad, a via pad or a fiducial. That removes guesswork for a fab’s CAM operator. If your fab’s upload tool asks for filename extensions instead, there is a Protel-extensions option. Use whichever the fab asks for, and do not mix them in one package.
• Check zone fills before plotting. Leave this on. It is the same check as above, built into the plot step.
• Subtract soldermask from silkscreen. This stops legend from printing over exposed pads. Whether the fab does it again on their side is their business, but a legend clipped on your side is one less surprise.
• Plot footprint values. Reference designators on silkscreen help whoever assembles and reworks the board. Values are usually clutter. Decide, rather than inheriting whatever the last project used.

Then open the output. Load the plotted files into a separate viewer, such as KiCad’s own Gerber Viewer, not the PCB editor. You are looking for things the editor tolerates and a viewer shows plainly:

1. Every expected layer is present: copper for each layer in the stackup, mask, paste if you need a stencil, legend, and the board outline on Edge.Cuts.
2. The outline is one closed shape. A gap in the outline is the classic reason a fab emails you.
3. Mask openings line up with pads, and no pad you meant to cover is open.
4. Nothing from a different project is in the folder. Old plots from a previous revision sitting next to new ones is how the wrong file gets uploaded.

If you are not sure whether your layout will survive assembly, our note on PCB layout mistakes that only show up at assembly covers the footprint and placement side.

Drill files

KiCad can write plated and non-plated holes into one file or two. That is a choice with a consumer on the other end: some fabs want them separate, some accept either. Ask, or read the upload instructions, and do not assume.

Two other settings matter more than people expect:

• Drill origin. The drill file’s coordinates are measured from a reference point. If you plot Gerbers with one origin and drill files with another, holes land in the wrong place relative to copper. Use the same origin for all of it. KiCad lets you set a drill/place file origin from the Place menu, and the same setting can be applied to placement files.
• Drill map. Generate the map file. It is a picture of every hole and its size. Compare it against the board by eye. A slot that became a row of round holes, or a mounting hole that ended up plated, shows up immediately.

Check the hole list against what you intended: via sizes, connector pins, mounting holes. Anything that looks like a stray size is usually a footprint from a library you forgot you had pulled in.

BOM and placement data for assembly

If the board is going to be assembled, two more files carry the work, and both are generated separately from the Gerbers. They are where most assembly questions begin.

The BOM. In KiCad’s schematic editor, a symbol has three exclusion flags, and they mean different things. Per the schematic editor manual:

• Exclude from bill of materials keeps the part out of BOM exports.
• Exclude from board means the symbol is schematic-only and no footprint goes onto the PCB.
• Do not populate means the part should not be attached, though its footprint stays on the board.

The failure is confusing the last two. A footprint kept for a future option should be marked do-not-populate, so it stays on the board but is not bought or placed. A test point or logo symbol should usually be out of the BOM. Check that the exported BOM does what you meant: every line has a manufacturer part number or a complete value, package and tolerance, and every do-not-populate item is flagged in a way your assembler will see. Our note on what to send for a PCB assembly quote lists what an assembler needs alongside the BOM.

The placement file. KiCad’s placement export has options that change its content: format, whether to include only SMD parts, whether to exclude do-not-populate and through-hole parts, whether to use the drill/place origin, one file or one per side, and how rotation is handled on the bottom side. Each of those can make a file that is internally correct and still wrong for the machine reading it.

Do not trust that the file is right because it exported. Check three or four parts. Pick an asymmetrical one, such as an SOIC or a polarized capacitor, one near each corner of the board, and one on the bottom side. Confirm position and rotation against the layout. Then ask your assembler what rotation and origin convention their programming expects. A footprint library’s pin-one orientation is a CAD convention. How a pick-and-place program reads a rotation angle is the assembler’s requirement, and the two do not always line up. An assembler who knows their own convention can usually tell you in one line what to adjust.

A short release routine

Run these in order, every time, even for a one-line change:

1. Update PCB from Schematic; confirm no differences.
2. Refill all zones.
3. Run DRC with parity check; resolve or justify each message.
4. Plot Gerbers and drill files into a clean, empty folder.
5. Open the result in a viewer; check layers, outline, mask, holes.
6. Export BOM and placement; spot-check parts against the layout.
7. Name the folder with the board revision, and keep a copy of exactly what was sent.

That last step pays for itself the first time a board comes back wrong and you need to know whether the fault was in your files or in the build.

How we handle it

We release from KiCad and review the output package as a separate step from the design review. If you have a project you are about to send out, or files a fab keeps bouncing, send us the project folder and the fabricator’s upload requirements, and we will tell you what we see.